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| ITF87056DQT TM Data Sheet July 2000 File Number 4813.3 5A, 20V, 0.045 Ohm, Dual P-Channel, 2.5V Specified Power MOSFET Packaging TSSOP-8 Features * Ultra Low On-Resistance - rDS(ON) = 0.045, VGS = -4.5V - rDS(ON) = 0.048, VGS = -4.0V - rDS(ON) = 0.077, VGS = -2.5V * 2.5V Gate Drive Capability * Gate to Source Protection Diode * Simulation Models - Temperature Compensated PSPICE(R) and SABERTM Electrical Models - Spice and SABER Thermal Impedance Models - www.intersil.com * Peak Current vs Pulse Width Curve 5 1 23 4 Symbol DRAIN1(1) OURCE1(2) SOURCE1(3) GATE1(4) (8) DRAIN2 (7) SOURCE2 (6) SOURCE2 (5) GATE2 * Transient Thermal Impedance Curve vs Board Mounting Area * Switching Time vs RGS Curves Ordering Information PART NUMBER ITF87056DQT PACKAGE TSSOP-8 87056 BRAND NOTE: When ordering, use the entire part number. ITF87056DQT2 is available only in tape and reel. Absolute Maximum Ratings TA = 25oC, Unless Otherwise Specified. ITF87056DQT UNITS V V V A A A A W mW/oC oC oC oC Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA = 25oC, VGS = -4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 25oC, VGS = -4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 100oC, VGS = -4.0V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA = 100oC, VGS = -2.5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: 1. TJ = 25oC to 125oC. 2. 62.5oC/W measured using FR-4 board with 0.50 in2 (322.6 mm2 ) copper pad at 1 second. 3. 230oC/W measured using FR-4 board with 0.0022 in2 (1.44 mm2) copper pad at 1000 seconds. -20 -20 12 5.0 5.0 3.0 2.5 Figure 4 2.0 16 -55 to 150 300 260 CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 1 CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. SABERTM is a trademark of Analogy Inc. PSPICE(R) is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000 ITF87056DQT Electrical Specifications PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS(TH) rDS(ON) VGS = VDS, ID = 250A Figure 10 ID = 5.0A, VGS = -4.5V Figures 8, 9 ID = 3.0A, VGS = -4.0V Figure 8 ID = 2.5A, VGS = -2.5V Figure 8 THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.50 in2 (322.6 mm2) (Note 2) Pad Area = 0.017 in2 (11.2 mm2) Figure 20 Pad Area = 0.0022 in2 (1.44 mm2) Figure 20 SWITCHING SPECIFICATIONS (VGS = -2.5V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time td(ON) tr td(OFF) tf VDD = -10V, ID = 2.5A VGS = -2.5V, RGS = 15 Figures 14, 18, 19 470 1240 700 775 ns ns ns ns 62.5 199 230 oC/W oC/W oC/W TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS BVDSS IDSS IGSS ID = 250A, VGS = 0V Figure 11 VDS = -20V, VGS = 0V VGS = 12V -20 - - -10 10 V A A -0.5 - 0.037 0.039 0.057 -1.5 0.045 0.048 0.077 V SWITCHING SPECIFICATIONS (VGS = -4.5V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at -2V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = -10V, VGS = 0V, f = 1MHz Figure 12 750 215 100 pF pF pF Qg(TOT) Qg(-2) Qg(TH) Qgs Qgd VGS = 0V to -4.5V VGS = 0V to -2V VGS = 0V to -0.5V VDD = -10V, ID = 5.0A, Ig(REF) = 1.0mA Figures 13, 16, 17 8.6 4.1 0.5 1.2 1.8 nC nC nC nC nC td(ON) tr td(OFF) tf VDD = -10V, ID = 5.0A VGS = -4.5V, RGS = 16 Figures 15, 18, 19 225 470 1200 800 ns ns ns ns Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = -5.0A ISD = -5.0A, dISD/dt = 10A/s ISD = -5.0A, dISD/dt = 10A/s TEST CONDITIONS MIN TYP -0.86 40 5 MAX UNITS V ns nC 2 ITF87056DQT Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) ID, DRAIN CURRENT (A) VGS = -4.5V, RJA = 62.5oC/W -4 -6 -2 VGS = -2.5V, RJA = 230oC/W FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE 2 1 THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 101 102 103 RJA = 230oC/W ZJA, NORMALIZED 0.1 0.01 SINGLE PULSE 0.001 10-5 10-4 10-3 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE -300 RJA = 230oC/W IDM, PEAK CURRENT (A) -100 VGS = -4.5V TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 VGS = -2.5V -10 150 - TA 125 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103 FIGURE 4. PEAK CURRENT CAPABILITY 3 ITF87056DQT Typical Performance Curves -100 (Continued) SINGLE PULSE TJ = MAX RATED TA = 25oC 100ms ID, DRAIN CURRENT (A) -15 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) -12 -10 1ms -1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) RJA -0.1 -1 = 230oC/W -10 VDS, DRAIN TO SOURCE VOLTAGE (V) -40 -9 -6 TJ = 150oC -3 TJ = -55oC TJ = 25oC 0 -0.5 -1.0 -1.5 -2.0 -2.5 VGS, GATE TO SOURCE VOLTAGE (V) 10ms FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. TRANSFER CHARACTERISTICS -15 VGS = -4.5V ID, DRAIN CURRENT (A) -12 VGS = -3V VGS = -2.5V VGS = -2V rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 100 90 80 ID = -5A 70 ID = -2.5A 60 50 40 30 -1 -2 -3 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX -9 -6 -3 VGS = -1.5V 0 0 -0.5 -1.0 -1.5 -2.0 -4 -5 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1.4 1.2 1.0 0.8 1.4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE 1.2 VGS = VDS, ID = -250A 1.0 0.8 VGS = -4.5V, ID = -5A 0.6 0.4 -80 0.6 -40 0 40 80 120 160 0.4 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 4 ITF87056DQT Typical Performance Curves 1.10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = -250A 1000 1.05 C, CAPACITANCE (pF) (Continued) 2000 VGS = 0V, f = 1MHz CISS = CGS + CGD COSS CDS + CGD 1.00 0.95 100 CRSS = CGD 0.90 -80 -40 0 40 80 120 160 50 -0.1 -1 VDS , DRAIN TO SOURCE VOLTAGE (V) -10 -20 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE -5 VGS , GATE TO SOURCE VOLTAGE (V) VDD = -10V 1500 VGS = -2.5V, VDD = -10V, ID = -2.5A SWITCHING TIME (ns) 1250 tr -4 -3 1000 tf 750 td(OFF) 500 td(ON) 250 -2 WAVEFORMS IN DESCENDING ORDER: ID = -5A ID = -2.5A 0 2 4 Qg, GATE CHARGE (nC) 6 8 -1 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT FIGURE 14. SWITCHING TIME vs GATE RESISTANCE 1500 VGS = -4.5V, VDD = -10V, ID = -5A 1250 SWITCHING TIME (ns) 1000 750 tr 500 td(ON) 250 0 td(OFF) tf 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () FIGURE 15. SWITCHING TIME vs GATE RESISTANCE 5 ITF87056DQT Test Circuits and Waveforms Qgs VDS RL 0 VGS = -0.5V -VGS VGS = -2V Qg(-2) VDD DUT Ig(REF) 0 Ig(REF) Qg(TOT) VGS = -4.5V Qg(TH) Qgd VDS VGS VDD + FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS tON td(ON) tOFF td(OFF) tr 0 10% tf 10% RL VDS VGS + 0V RGS -VGS DUT 0 VDS 90% 90% 10% 50% VGS PULSE WIDTH 90% 50% FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. ( T JM - T A ) P DM = -----------------------------R JA 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM . (EQ. 1) In using surface mount devices such as the TSSOP-8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 6 ITF87056DQT Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. R JA = 138.68 - 14.95 x 300 250 R, RJA (oC/W) 200 150 100 50 R = 63.46 - 15.08 * ln (AREA) 0 0.001 0.01 0.1 1 AREA, TOP COPPER AREA (in2) PER DIE 230 oC/W - 0.0022in2 RJA = 138.68- 14.95 * ln (AREA) 199 oC/W - 0.017in2 R1 = R2 = 98oC/W TJ1 and TJ2 define the junction temperature of the respective die. Similarly, P1 and P2 define the power dissipated in each die. The steady state junction temperature can be calculated using Equation 4 for die 1 and Equation 5 for die 2. Example: To calculate the junction temperature of each die when die 2 is dissipating 0.5W and die 1 is dissipating 0W. The ambient temperature is 70oC and the package is mounted to a top copper area of 0.1 square inches per die. Use Equation 4 to calculate TJ1 and Equation 5 to calculate TJ2 . . ln ( Area ) (EQ. 2) T J1 = P 1 R JA + P 2 R + T A (EQ. 4) oC/W) + (0.5 Watts)(98oC/W) + 70oC TJ1 = (0 Watts)(173 TJ1 = 119oC T J2 = P 2 R JA + P 1 R + T A (EQ. 5) TJ2 = (0.5 Watts)(173oC/W) + (0 Watts)(98oC/W) + 70oC FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA TJ2 = 156.5oC The transient thermal impedance (ZJA) is also affected by varied top copper board area. Figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. While Equation 2 describes the thermal resistance of a single die, several devices are offered with two die in the TSSOP-8 package. The dual die TSSOP-8 package introduces an additional thermal component, thermal coupling resistance, R. Equation 3 describes R as a function of the top copper mounting pad area. R = 63.46 - 15.08 x ln ( Area ) (EQ. 3) The thermal coupling resistance vs copper area is also graphically depicted in Figure 20. It is important to note the thermal resistance (RJA) and thermal coupling resistance (R) are equivalent for both die. For example at 0.1 square inches of copper: RJA1 = RJA2 = 173oC/W 200 COPPER BOARD AREA - DESCENDING ORDER 0.02 in2 0.14 in2 0.26 in2 0.38 in2 100 0.50 in2 IMPEDANCE (oC/W) ZJA, THERMAL 150 50 0 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103 FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA 7 ITF87056DQT PSPICE Electrical Model .SUBCKT ITF87056DQT 2 1 3 ; CA 12 8 9.3e-10 CB 15 14 10.5e-10 CIN 6 8 6.3e-10 ESG LDRAIN + 5 RLDRAIN EBREAK ESLC 50 DBODY + 17 18 DRAIN 2 RSLC1 51 REV January 2000 RSLC2 DPLCAP EVTHRES + 19 8 6 LGATE EVTEMP RGATE 9 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 1.29e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD GATE 1 RLGATE - 20 DESD1 91 DESD2 18 + 22 CIN RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 17e-3 RGATE 9 20 685 RLDRAIN 2 5 10 RLGATE 1 9 10.4 RLSOURCE 3 7 1.29 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 17e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17 - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),2.1))} .MODEL DBODYMOD D (IS = 2.4e-11 IKF = 0.08 RS = 1.55e-2 TRS1 = 1.7e-3 TRS2 = 2e-6 CJO = 3.2e-10 TT = 3e-9 M = 0.4) .MODEL DBREAKMOD D (RS = 2e-1 TRS1 = 5e-3 TRS2 = 2e-6) .MODEL DESD1MOD D (BV = 14.1 TBV1 = -1.21e-3 N = 9 RS = 160) .MODEL DESD2MOD D (BV = 14 TBV1 = -1.21e-3 N = 9 RS = 180) .MODEL DPLCAPMOD D (CJO = 3.7e-10 IS = 1e-30 N = 10 M = 0.5 VJ = 0.45) .MODEL MMEDMOD PMOS (VTO = -0.95 KP = 1.7 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 685 RS = 0.1) .MODEL MSTROMOD PMOS (VTO = -1.21 KP = 43.7 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD PMOS (VTO = -0.76 KP = 0.06 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 6850 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 8.5e-4 TC2 = -1.1e-6) .MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = -1.5e-5) .MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = 5e-4 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = 1.2e-3 TC2 = 2e-6) .MODEL RVTEMPMOD RES (TC1 = -3.5e-4 TC2 = -1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = 2.5 VON = 1.5 VON = 0.8 VON = 0.1 VOFF= 1.5) VOFF= 2.5) VOFF= 0.1) VOFF= 0.8) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 8 - EBREAK 5 11 17 18 -28.75 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 5 10 8 6 1 EVTHRES 6 21 19 8 1 EVTEMP 6 20 18 22 1 5 51 + DBODY 5 7 DBODYMOD DBREAK 7 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 6 DPLCAPMOD 10 - 8 6 - RDRAIN 21 16 MWEAK MMED MSTRO 8 RSOURCE DBREAK 11 LSOURCE 7 RLSOURCE SOURCE 3 RBREAK 18 RVTEMP 19 VBAT + 8 22 RVTHRES ITF87056DQT SABER Electrical Model REV January 2000 template ITF87056DQT n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.4e-11, ikf = 0.08, cjo = 3.2e-10, tt = 3e-9, m = 0.4, rs = 1.55e-2, trs1 = 1.7e-3, trs2 = 2e-6) dp..model dbreakmod = (rs = 2e-1, trs1 = 5e-3, trs2 = 2e-6) dp..model desd1mod = (bv = 14.1, tbv1 = -1.21e-3, nl = 9, rs = 160) dp..model desd2mod = (bv = 14, tbv1 = -1.21e-3, nl = 9, rs = 180) dp..model dplcapmod = (cjo = 3.7e-10, isl = 10e-30, nl = 10, m = 0.5, vj = 0.45) m..model mmedmod = (type=_p, vto = -0.95, kp = 1.7, is = 1e-30, tox = 1, rs = 0.1) m..model mstrongmod = (type=_p, vto = -1.21, kp = 43.7, is = 1e-30, tox = 1) m..model mweakmod = (type=_p, vto = -0.76, kp = 0.06, is = 1e-30, tox = 1, rs = 0.1) ESG sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 2.5, voff = 1.5) 5 -8+ sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = 1.5, voff = 2.5) 6 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.8, voff = 0.1) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.1, voff = 0.8) 10 c.ca n12 n8 = 9.3e-10 c.cb n15 n14 = 10.5e-10 c.cin n6 n8 = 6.3e-10 dp.dbody n5 n7 = model=dbodymod dp.dbreak n7 n11 = model=dbreakmod dp.desd1 n91 n9 = model=desd1mod dp.desd2 n91 n7 = model=desd2mod dp.dplcap n10 n6 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.04e-9 l.lsource n3 n7 = 1.29e-10 GATE 1 RLGATE 91 DESD2 DPLCAP EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A S2A RBREAK 13 8 S1B 13 + EGS 6 8 EDS 14 13 S2B CB + 5 8 14 IT 15 17 18 RVTEMP 19 7 SOURCE 3 RSLC1 51 RSLC2 ISCL 50 RDRAIN 16 21 MWEAK MMED DBODY DBREAK LDRAIN DRAIN 2 RLDRAIN + EBREAK 17 18 - 11 LGATE RGATE 9 EVTEMP - 20 DESD1 18 + 22 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 8.5e-4, tc2 = -1.1e-6 res.rdrain n50 n16 = 17e-3, tc1 = 9e-3, tc2 = -1.5e-5 res.rgate n9 n20 = 685 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10.4 res.rlsource n3 n7 = 1.29 res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 17e-3, tc1 = 5e-4, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -3.5e-4, tc2 = -1e-6 res.rvthres n22 n8 = 1, tc1 = 1.2e-3, tc2 = 2e-6 spe.ebreak n5 n11 n17 n18 = -28.75 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n5 n10 n8 n6 = 1 spe.evtemp n6 n20 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 12 CA VBAT + - - 8 RVTHRES 22 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/120))** 2.1)) } } 9 ITF87056DQT SPICE Thermal Model REV 26 January 2000 ITF87056DQT Copper Area = 0.50 in2 CTHERM1 th 8 6.7e-4 CTHERM2 8 7 2.2e-3 CTHERM3 7 6 5.0e-3 CTHERM4 6 5 8.6e-3 CTHERM5 5 4 2.2e-2 CTHERM6 4 3 0.08 CTHERM7 3 2 0.32 CTHERM8 2 tl 1.9 RTHERM1 th 8 0.267 RTHERM2 8 7 0.893 RTHERM3 7 6 2.23 RTHERM4 6 5 14.28 RTHERM5 5 4 21.42 RTHERM6 4 3 23.0 RTHERM7 3 2 27.0 RTHERM8 2 tl 29.0 th JUNCTION RTHERM1 8 CTHERM1 RTHERM2 7 CTHERM2 RTHERM3 6 CTHERM3 RTHERM4 CTHERM4 5 SABER Thermal Model Copper Area = 0.50 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 6.7e-4 ctherm.ctherm2 8 7 = 2.2e-3 ctherm.ctherm3 7 6 = 5.0e-3 ctherm.ctherm4 6 5 = 8.6e-3 ctherm.ctherm5 5 4 = 2.2e-2 ctherm.ctherm6 4 3 = 0.08 ctherm.ctherm7 3 2 = 0.32 ctherm.ctherm8 2 tl = 1.9 rtherm.rtherm1 th 8 = 0.267 rtherm.rtherm2 8 7 = 0.893 rtherm.rtherm3 7 6 = 2.23 rtherm.rtherm4 6 5 = 14.28 rtherm.rtherm5 5 4 = 21.42 rtherm.rtherm6 4 3 = 23.0 rtherm.rtherm7 3 2 = 27.0 rtherm.rtherm8 2 tl = 29.0 } RTHERM5 CTHERM5 4 RTHERM6 3 CTHERM6 RTHERM7 2 CTHERM7 RTHERM8 CTHERM8 tl AMBIENT TABLE 1. THERMAL MODELS COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.02 in2 0.07 0.15 0.68 22.8 39.5 56 0.14 in2 0.05 0.24 1.3 21 30 45 0.26 in2 0.06 0.25 1.6 21 32 38 0.38 in2 0.07 0.28 2.0 25 30 34 0.50 in2 0.08 0.32 1.9 23 27 29 10 ITF87056DQT MO-153AA (TSSOP-8) 8 LEAD JEDEC MO-153AA TSSOP PLASTIC PACKAGE E E1 8 A A1 INCHES SYMBOL A MIN 0.041 0.002 0.010 0.005 0.114 0.244 0.170 0.122 0.260 0.177 MAX 0.047 0.006 0.012 MILLIMETERS MIN 1.05 0.05 0.25 0.127 2.90 6.20 4.30 3.10 6.60 4.50 MAX 1.20 0.15 0.30 NOTES 2 3 4 e D 5 4 A1 b c b c D E E1 e 0.004 IN 0.10mm 0.025 BSC 0.020 0.028 0.65 BSC 0.50 0.70 L 0o-8o 0.015 0.4 0.035 0.9 L 0.025 0.65 0.232 5.9 0.077 1.95 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC MO-153AA outline dated 10-97. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Interlead flash and protrusions shall not exceed 0.010 inches (0.25mm) per side. 4. "L" is the length of terminal for soldering. 5. Controlling dimension: Millimeter 6. Revision 3 dated: 5-00. MO-153AA (TSSOP-8) 12mm TAPE AND REEL 17.4mm 1.5mm DIA. HOLE 4.0mm 2.0mm 1.75mm C L 12mm 330mm 100mm 13mm 8.0mm USER DIRECTION OF FEED 13.4mm COVER TAPE GENERAL INFORMATION 1. 3000 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS. 11 ITF87056DQT All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369 12 |
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